NBTI-aware design of NoC buffers

Network-on-Chips (NoC) play a central role in determining performance and reliability in current and future multi-core architectures. Continuous scaling of CMOS technology enable widespread adoption of multi-core architectures but, unfortunately, poses severe concerns regarding failures. Process variation (PV) is worsening the scenario, decreasing device lifetime and performance predictability during chip fabrication. This paper proposes two solutions exploiting power-gating to cope with NBTI effects in NoC buffers. The techniques are evaluated with respect to a variable number of virtual channels (VCs), in the presence of process variation. Moreover, power gating delay overhead is accounted. Experiments reveal a net NBTI Vth saving up to 54.2% against the baseline NoC, with an area overhead below 5%.

[1]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Priyadarsan Patra,et al.  Impact of Process and Temperature Variations on Network-on-Chip Design Exploration , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[3]  Tao Li,et al.  Architecting reliable multi-core network-on-chip for small scale processing technology , 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

[4]  Arnab Banerjee,et al.  A Power and Energy Exploration of Network-on-Chip Architectures , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[5]  Sani R. Nassif,et al.  Characterizing Process Variation in Nanometer CMOS , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  Niraj K. Jha,et al.  GARNET: A detailed on-chip network model inside a full-system simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[7]  Yu-Guang Chen,et al.  NBTI-aware power gating design , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[8]  Lin Li,et al.  Proactive NBTI mitigation for busy functional units in out-of-order microprocessors , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  Chita R. Das,et al.  On the Effects of Process Variation in Network-on-Chip Architectures , 2010, IEEE Transactions on Dependable and Secure Computing.

[10]  William Fornaciari,et al.  HANDS: heterogeneous architectures and networks-on-chip design and simulation , 2012, ISLPED '12.

[11]  Puneet Gupta,et al.  On the efficacy of NBTI mitigation techniques , 2011, 2011 Design, Automation & Test in Europe.

[12]  David Blaauw,et al.  Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor , 2011, IEEE Trans. Circuits Syst. I Regul. Pap..

[13]  Sudhanva Gurumurthi,et al.  A multi-level approach to reduce the impact of NBTI on processor functional units , 2010, GLSVLSI '10.

[14]  Robert P. Dick,et al.  Minimization of NBTI performance degradation using internal node control , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Yu Cao,et al.  Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.