The 5/sup th/ generation highly rugged planar IGBT using sub-micron process technology

In this paper, a new optimized 600 V class, highly rugged 5/sup th/ generation IGBT with a very fine ladder structure of n+ emitter realized by sub-micron wafer process technology is proposed and its performance has been demonstrated for the first time.

[1]  Mutsuhiro Mori,et al.  An insulated gate bipolar transistor with a self-aligned DMOS structure , 1988, Technical Digest., International Electron Devices Meeting.

[2]  Gourab Majumdar,et al.  High-functionality compact intelligent power unit (IPU) for EV/HEV applications , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[3]  H. Hagino,et al.  A study on the IGBT's turn-off failure and inhomogeneous operation , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[4]  Gourab Majumdar,et al.  A new generation high speed low loss IGBT module , 1992, Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics.

[5]  J. Yamashita,et al.  An experimental and numerical study on the forward biased SOA of IGBTs , 1996 .

[6]  W. Kiffe,et al.  A low loss/highly rugged IGBT-generation based on a self aligned process with double implanted n/n/sup +/-emitter , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[7]  K. Sakurai,et al.  Analysis on device structures for next generation IGBT , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[8]  Masahito Otsuki,et al.  Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).