Fast CR-SRAM Using New Charge-Recycling Scheme

In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.

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