MITIGATION OF RANDOM AND DETERMINISTIC NOISE IN MIXED SIGNAL SYSTEMS WITH EXAMPLES IN FREQUENCY SYNTHESIZER SYSTEMS by THOMAS WESTON BURRESS

RF frequency synthesizer systems are prevalent in today’s electronics. In a synthesizer there is a sensitive analog oscillator that may be affected by two different types of noise. The first is random noise injection from active devices. This results in phase noise in the synthesizer’s spectrum. The second noise source is deterministic. A digital frequency divider with high-amplitude switching is an example of such a deterministic source. This noise enters the system through various forms of electric or magnetic field coupling and manifests itself as spurs or pulling. Both forms of noise can adversely affect system performance. We will first summarize methods for reducing noise. These already known steps have to do with layout techniques, device geometry, and general synthesizer topologies. Then we will show ways to isolate noisy interfering circuits from the sensitive analog systems. Finally, we present some considerations for reducing the effects of random noise. A power supply filter can improve the effects of deterministic noise such as undesired signals on the supply line. We show several ways to improve the rejection of high frequency supply noise (characterized by the power supply rejection ratio or PSRR) through the design of a voltage regulator. The emphasis is on new techniques for obtaining good PSRR at S-band frequencies and above. To validate the techniques, we designed a regulator in Peregrine Semiconductor’s .25μm ULTRA CMOS Silicon on Sapphire process. It produces a 2.5V output with an input ranging from 2.6V to 5V and has a maximum current sourcing of 70mA. The regulator’s low drop out performance is 60mV with no load and it achieves a power supply ripple reduction of 29.8 dB at 500 MHz. To address random noise in synthesizers, the thesis provides preliminary investigation of an oscillator topology change that has been proposed in the literature. This proposed change reduces the phase noise of the oscillator within the overall system. A differential cross-coupled design is the usual topology of choice, but it is not optimal for noise performance. We investigate current noise injection in the traditional design and present an updated design that uses a differential Colpitts oscillator as an alternative to classic cross-coupled designs.

[1]  Sangwon Han,et al.  A Low Noise CMOS Low Dropout Regulator with an Area-Efficient Bandgap Reference , 2009, IEICE Trans. Electron..

[2]  T. Nakamura,et al.  A Wide-tuning-range VCO with Small VCO-gain Fluctuation for Multi-band W-CDMA RFIC , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[3]  Hae-Seung Lee,et al.  SESSION 14: ANALOG PROCESSORS THPM 14.1: A 200MHz CMOS Phase-Locked Loop with Dual Phase Detectors* , 1989 .

[4]  Zhiliang Chen,et al.  A Linear Voltage Regulator for PLL in SOC Application , 2006, 2006 International Conference on Wireless Communications, Networking and Mobile Computing.

[5]  J. Choma,et al.  A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter , 2001, IEEE J. Solid State Circuits.

[6]  S. Gondi,et al.  Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture , 2009, IEEE Journal of Solid-State Circuits.

[7]  C. Yue,et al.  On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's , 1997, Symposium 1997 on VLSI Circuits.

[8]  Gabriel A. Rincón-Mora,et al.  A low dropout, CMOS regulator with high PSR over wideband frequencies , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[9]  R. Wrathall,et al.  The design of an automotive low drop out regulator IC utilizing a depletion mode high voltage DMOS pass element , 1994, Proceedings of 1994 IEEE Workshop on Power Electronics in Transportation.

[10]  Michael S. McCorquodale,et al.  Study and simulation of CMOS LC oscillator phase noise and jitter , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[11]  A. Hajimiri,et al.  Design issues in CMOS differential LC oscillators , 1999, IEEE J. Solid State Circuits.

[12]  K. B. Albers Noise characterization of transistors in 0.25μm and 0.5μm silicon-on-sapphire processes , 2010 .

[13]  M. Mizuno,et al.  Elastic-Vt CMOS circuits for multiple on-chip power control , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[15]  A low drop-out voltage regulator with multiple enable control , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[16]  Franco Maloberti,et al.  A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[17]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[18]  Ngai Wong,et al.  A Sub-1 V, 26 $\mu$W, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Pavan Kumar Hanumolu,et al.  Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  C. Piguet,et al.  A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[21]  T.H. Lee,et al.  Phase noise in CMOS differential LC oscillators , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[22]  У Отт Генри,et al.  Методы подавления шумов и помех в электронных системах. (Noise reduction techniques in electronic systems) , 1979 .

[23]  Zou Xuecheng,et al.  A High Precision CMOS Current-mode Band-gap Voltage Reference , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.