Cycle time estimation for wafer fab with engineering lots

Due to the interaction between the process complexity and equipment diversity in a wafer fab, it is rather difficult to estimate the material flow time of wafer lots. Facing competition, it is common for a wafer fab to produce a certain quantity of engineering lots. However, introducing engineering lots into the factory will increase the complexity of the material flow control and the difficulty in cycle time estimation. The purpose of this paper is to develop cycle time estimation algorithms for a wafer fab by analyzing the material flow characteristics. Simulation results have shown that the algorithm is capable of generating satisfactory cycle time estimations with or without existing engineering lots.

[1]  R. G. Petrakian,et al.  Trade-offs in cycle time management: hot lots , 1992 .

[2]  R. W. Atherton,et al.  Experience in simulating wafer fabs in the USA and Japan , 1990, IEEE/SEMI International Symposium on Semiconductor Manufacturing Science.

[3]  Yadati Narahari,et al.  Modeling the effect of hot lots in semiconductor manufacturing systems , 1997 .

[4]  John W. Fowler,et al.  Real-time control of multiproduct bulk-service semiconductor manufacturing processes , 1992 .

[5]  D. Martin,et al.  How the law of unanticipated consequences can nullify the theory of constraints: The case for balanced capacity in a semiconductor manufacturing line , 1997, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 97 Proceedings.

[6]  B. Grigsby,et al.  Throughput time forecasting model , 1997, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 97 Proceedings.

[7]  Yeong-Dae Kim,et al.  Due-date based scheduling and control policies in a multiproduct semiconductor wafer fabrication facility , 1998 .

[8]  Hw Huang,et al.  The block-based cycle time estimation algorithm for wafer fabrication factories , 1999 .

[9]  Mauricio G. C. Resende,et al.  Closed-loop job release control for VLSI circuit manufacturing , 1988 .

[10]  S. C. Wood.  Cost and cycle time performance of fabs based on integrated single-wafer processing , 1997 .

[11]  D. J. Miller.  Implementing the results of a manufacturing simulation in a semiconductor line , 1989, WSC '89.

[12]  William L. Maxwell,et al.  Theory of scheduling , 1967 .

[13]  C. R. Glassey,et al.  Dynamic batching heuristic for simultaneous processing , 1991 .

[14]  J. A. Cunningham.  The use and evaluation of yield models in integrated circuit manufacturing , 1990 .

[15]  D. Fronckowiak,et al.  Using discrete event simulation to analyze the impact of job priorities on cycle time in semiconductor manufacturing , 1996, IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings.

[16]  Frederick S. Hillier,et al.  Introduction of Operations Research , 1967 .

[17]  Ali Tamer Unal,et al.  A probabilistic cost-based due date assignment model for job shops , 1993 .

[18]  Lawrence M. Wein,et al.  Scheduling semiconductor wafer fabrication , 1988 .

[19]  S. T. Enns,et al.  A dynamic forecasting model for job shop flowtime prediction and tardiness control , 1995 .

[20]  Eric R. Zieyel.  Operations research : applications and algorithms , 1988 .

[21]  Robert W. Atherton,et al.  Wafer Fabrication: Factory Performance and Analysis , 1995 .

[22]  Frederick S. Hillier,et al.  Introduction of Operations Research , 1967 .

[23]  Kevin J. Dooley,et al.  Dynamic rules for due-date assignment , 1991 .