Intelligence implementation on silicon based on four-terminal device electronics☆

Abstract We will propose the concept of a “four-terminal device” which functionally surpasses three-terminal devices like MOSFET's and bipolar transistors in the ability of controlling the current flowing through a device. The enhanced functionality at the very elemental transistor level is quite essential in creating intelligent functions at the system level. A neuron MOSFET (νMOS), a multiple-input-terminal floating-gate device, is taken as an example of a four-terminal device and the implementation of new-architecture electronic circuits is demonstrated. The binary-multivalue-analog merged hardware algorithms conducted by vMOS circuits provide a highly flexible data processing scheme while assuring the accuracy of binary digital computation, thus presenting a very promising approach to implementing human-intelligence electronic systems on silicon.

[1]  T. Ohmi.  ULSI reliability through ultraclean processing , 1993, Proc. IEEE.

[2]  Fujio Masuoka,et al.  Stacked-Gate Avalanche-Injection Type MOS (SAMOS) Memory , 1972 .

[3]  W. Pitts,et al.  A Logical Calculus of the Ideas Immanent in Nervous Activity (1943) , 2021, Ideas That Created the Future.

[4]  T. Ohmi,et al.  Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[5]  Masashi Horiguchi,et al.  An experimental 220 MHz 1 Gb DRAM , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[6]  Tadashi Shibata,et al.  Hardware-Oriented Learning Algorithm Implemented on Silicon Using Neuron MOS Technology , 1994 .

[7]  Tadashi Shibata,et al.  Neuron MOS winner-take-all circuit and its application to associative memory , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  G. Cauwenberghs,et al.  A Charge-Based CMOS Parallel Analog Vector Quantizer , 1994, NIPS 1994.

[9]  Gordon E. Moore,et al.  Progress in digital integrated electronics , 1975 .

[10]  Tadahiro Ohmi,et al.  Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications , 1993 .

[11]  S. Sze,et al.  A floating gate and its application to memory devices , 1967 .

[12]  Tadashi Shibata,et al.  A neuron-MOS neural network using self-learning-compatible synapse circuits , 1995, IEEE J. Solid State Circuits.

[13]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[14]  F. Masuoka,et al.  Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure , 1976, IEEE Transactions on Electron Devices.

[15]  H. Tango,et al.  Avalanche-Injection MOS Read-Only-Memory , 1971 .

[16]  Tadashi Shibata,et al.  An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning Neuron-MOS neural networks , 1993 .

[17]  Toshiro Itani,et al.  A 1-Gb DRAM for file applications , 1995 .

[18]  Tadahiro Ohmi,et al.  Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks , 1995 .

[19]  Tadashi Shibata,et al.  Neuron-MOS multiple-valued memory technology for intelligent data processing , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[20]  T. Shibata,et al.  A New EEPROM Cell with Dual Control Gate Structure , 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.

[21]  S. Inoue,et al.  Optimum design of dual control gate cell for high density EEPROMs , 1983 .

[22]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[23]  Teuvo Kohonen,et al.  The self-organizing map , 1990, Neurocomputing.

[24]  Tadashi Shibata,et al.  Real-time reconfigurable logic circuits using neuron MOS transistors , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[25]  Tadashi Shibata,et al.  Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation , 1993 .

[26]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[27]  D. Frohman-Bentchkowsky,et al.  A fully-decoded 2048-bit electrically-programmable MOS ROM , 1971 .

[28]  D. Frohman-Bentchkowsky.  Memory Behavior in a Floating-Gate Avalanche-Injection MOS (famos) Structure , 1971 .

[29]  Tadashi Shibata,et al.  The Concept of Four-Terminal Devices and Its Significance in the Implementation of Intelligent Integrated Circuits , 1994 .

[30]  Tadahiro Ohmi,et al.  A self-learning neural-network LSI using neuron MOSFETs , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.