A methodology for design, modeling, and analysis of networks-on-chip

In this paper, we present an architecture-level methodology for modeling, analysis, and design of networks-on-chip (NoC), and we tested it through two NoC designs. The methodology can quickly and accurately estimate the performance, power, and area of a NoC at architecture level, and it can efficiently model different types of NoCs. The methodology can be easily incorporated into a traditional design flow. Using this methodology, we designed a bus-based NoC and a crossbar-based NoC for a high-performance embedded video SoC design in a 0.13 /spl mu/m technology. We analyzed their performance, powers and area in detail. We find that the crossbar-based NoC not only has 62.5% higher performance but also consumes 82% less power compared to the bus-based NoC. The crossbar-based NoC uses 88% less silicon area and 123% more metal area than the bus-based NoC. This methodology also helped to refine the crossbar-based NoC design and save additional 57% power. Our study shows that interconnections dominate power and area in NoC designs, and only comparing the logic circuits of NoCs will give wrong conclusions.