A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

A 14 b pipeline ADC is realized in 90 nm CMOS at a 1.2 V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital background calibration of non-linearity. The ADC achieves 73 dB SNR and 91 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.7 pJ/conv.

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