Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

[1]  Zhe Zhang,et al.  Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Jai-Ming Lin,et al.  Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Kaustav Banerjee,et al.  Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[4]  Xin-She Yang,et al.  Introduction to Algorithms , 2021, Nature-Inspired Optimization Algorithms.

[5]  Chin-Long Wey,et al.  Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  A. Hastings.  The Art of Analog Layout , 2000 .

[7]  Evangeline F. Y. Young,et al.  Analog placement with common centroid constraints , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Chun-Yu Lin,et al.  Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  G. Knoblinger,et al.  Analog design challenges and trade-offs using emerging materials and devices , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[10]  Evangeline F. Y. Young,et al.  Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Evangeline F. Y. Young,et al.  Analog placement with common centroid and 1-D symmetry constraints , 2009, 2009 Asia and South Pacific Design Automation Conference.

[12]  Sheqin Dong,et al.  Multi-stage analog placement with various constraints , 2010, 2010 International Conference on Communications, Circuits and Systems (ICCCAS).

[13]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[14]  Liesbeth Witters,et al.  Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession , 2010 .

[15]  T.S. Fiez,et al.  Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations , 1999, IEEE Journal of Solid-State Circuits.

[16]  Tan Yan,et al.  Formulating the empirical strategies in module generation of analog MOS layout , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[17]  F. Gámiz,et al.  Two-Dimensional Monte Carlo Simulation of DGSOI MOSFET Misalignment , 2012, IEEE Transactions on Electron Devices.

[18]  Chin-Long Wey,et al.  Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits , 2013, TODE.

[19]  P. Tiwari,et al.  A rigorous simulation based study of gate misalignment effects in gate engineered double-gate (DG) MOSFETs , 2013 .

[20]  Melanie Hartmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[21]  Di Long,et al.  Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[22]  Dimitri Linten,et al.  The Potential of FinFETs for Analog and RF Circuit Applications , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Mark Po-Hung Lin,et al.  Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Jai-Ming Lin,et al.  Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[25]  Yao-Wen Chang,et al.  Thermal-driven analog placement considering device matching , 2009, 2009 46th ACM/IEEE Design Automation Conference.