Debug support for complex systems on-chip: a review

The introduction of complex systems-on-chip (SoC) devices with multiple processor cores presents new challenges for embedded systems developers. Novel development tools specifically targeting complex SoC will help overcome these challenges, but are typically limited by inadequate debug support facilities within the SoC. High-quality debug support with advanced features is essential to take full advantage of complex SoC devices in challenging applications while simultaneously reducing development time. Here, existing strategies for providing comprehensive SoC debug support targeting hard real-time applications, such as automotive control, where development challenges are overwhelming are reviewed. This overview includes an evaluation of the available solutions and their suitability for use with the next generation of complex SoC based on multiple processor cores. It is shown that many existing solutions do not readily permit developers to take advantage of the complex features integrated into the next generation of SoC. The essential features of debug support for multiple processor core SoCs are summarised and discussed. Recommendations are made for SoC designers and for the future direction of research in this area, with the aim of providing a more suitable foundation for new development tools. Such tools are badly needed for all hard real-time embedded systems and are paramount to managing the development complexity introduced by SoC devices with multiple highly interactive processor cores and active peripherals.

[1]  Bart Vermeulen,et al.  Silicon debug: scan chains alone are not enough , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  Ing-Jer Huang,et al.  ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers , 1999, DAC '99.

[3]  Steven F. Oakland Position statement: TAPs all over my chips , 2002, Proceedings. International Test Conference.

[4]  Bart Vermeulen,et al.  IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips , 2002, Proceedings. International Test Conference.

[5]  Tulika Mitra,et al.  Using formal techniques to debug the AMBA system-on-chip bus protocol , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Klaus D. McDonald-Maier,et al.  Debug support strategy for systems-on-chips with multiple processor cores , 2006, IEEE Transactions on Computers.

[7]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[8]  Sandeep Kumar Goel,et al.  Design for debug: catching design errors in digital chips , 2002, IEEE Design & Test of Computers.

[9]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[10]  Brian J. Smith Fast prototyping , 1988 .

[11]  Heinrich Meyr,et al.  A framework for fast hardware-software co-simulation , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[12]  Lee Whetsel,et al.  An IEEE 1149.1 based test access architecture for ICs with embedded cores , 1997, Proceedings International Test Conference 1997.

[13]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[14]  Sandeep Kumar Goel,et al.  Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips , 2002, Proceedings. International Test Conference.

[15]  Klaus D. McDonald-Maier,et al.  Measuring Determinism in Real-Time Embedded Systems using Cached Processors , 2005, ESA.

[16]  C. Melear Using background modes for testing, debugging and emulation of microcontrollers , 1997, WESCON/97 Conference Proceedings.

[17]  D. Huffman A Method for the Construction of Minimum-Redundancy Codes , 1952 .

[18]  Harry Siebert,et al.  Debug support, calibration and emulation for multiple processor and powertrain control SoCs [automotive applications] , 2005, Design, Automation and Test in Europe.

[19]  Moon-Key Lee,et al.  Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[20]  Klaus D. Maier On-chip debug support for embedded Systems-on-Chip , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[21]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[22]  Harry Siebert,et al.  Embedded System Tool to Support Debugging, Calibration, Fast Prototyping and Emulation , 2004 .

[23]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[24]  Jitendra Khare,et al.  Test and debug of networking SoCs-a case study , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[25]  Stephen Pateras Embedded diagnosis IP , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.