Explorations of sequential ATPG using Boolean satisfiability
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[1] Tracy Larrabee,et al. Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.
[2] Tracy Larrabee,et al. Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Kwang-Ting Cheng. Recent advances in sequential test generation , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.
[4] Alberto L. Sangiovanni-Vincentelli,et al. Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Tracy Larrabee,et al. Test pattern generation for current testable faults in static CMOS circuits , 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.
[6] Miron Abramovici,et al. FREEZE: a new approach for testing sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[7] Peter Muth,et al. A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.
[8] Melvin A. Breuer. A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits , 1971, IEEE Transactions on Computers.
[9] Fabio Somenzi,et al. Fast sequential ATPG based on implicit state enumeration , 1991, 1991, Proceedings. International Test Conference.
[10] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[11] Janak H. Patel,et al. HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..
[12] Srinivas Devadas,et al. Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..