Sensitivity analysis of C-V global variability for 28 nm FD-SOI

This work describes a statistical model for the C-V global variability of 28 nm FD-SOI using the sensitivities of the capacitance to each process parameter calculated using Leti-UTSOI compact model. The percentage contribution of each process parameter to the total C-V variation is explored to identify the dominant source of variation at different bias conditions. The proposed model provides an alternate method to directly extract the variance of the process parameters from the measured C-V variability.

[1]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[2]  O. Rozeau,et al.  Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description , 2015, IEEE Transactions on Electron Devices.

[3]  Kelin J. Kuhn,et al.  CMOS transistor scaling past 32nm and implications on variation , 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

[4]  Gérard Ghibaudo,et al.  Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI , 2017, 2017 International Conference of Microelectronic Test Structures (ICMTS).

[5]  Sylvain Barraud,et al.  Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs , 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).