A silicon platform with Through-silicon vias for heterogeneous RF 3D modules

This paper presents a silicon platform with Through-silicon vias (TSV) interconnects for Radio-Frequency applications, implemented in a via-last integration scheme. As it is aimed at transmitting a wide range of signals, it is mandatory to accurately evaluate frequency dependent loss of TSV. To achieve attractive RF performances, the silicon platform is carried out on High-Resistivity (HR) substrates. Indeed, silicon conductivity is a material property that has major influence on TSV electrical characteristics. Fabrication, design and characterization of wideband wave-guided TSV transition are detailed. Measurements and three-dimensional electromagnetic (3D EM) simulations demonstrate significant influence of parasitic coupling through the substrate. Finally, technological and design optimizations are highlighted to reduce impedance mismatch and substrate influence.

[1]  L. Di Cioccio,et al.  Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs , 2008, 2008 IEEE International Electron Devices Meeting.

[2]  T. Kurihara,et al.  A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect , 2008, 2008 58th Electronic Components and Technology Conference.

[3]  P. Descamps,et al.  Physical implementation of 3D integrated solenoids within silicon substrate for hybrid IC applications , 2009, 2009 European Microwave Conference (EuMC).

[4]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[5]  A. Shibuya,et al.  Si interposers integrated with SrTiO3 thin film decoupling capacitors and through-Si-vias , 2008, 2008 IEEE 9th VLSI Packaging Workshop of Japan.

[6]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[7]  P. Mclarty,et al.  Reactive ion etching induced damage with gas mixtures CHF3/O2 and SF6/O2 , 1995 .

[8]  Vincent Fusco,et al.  SiO/sub 2/ interface layer effects on microwave loss of high-resistivity CPW line , 1999 .

[9]  V. Lee,et al.  Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[10]  R. Anciant,et al.  Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results , 2008, 2008 10th Electronics Packaging Technology Conference.

[11]  S. Seki,et al.  Coplanar Waveguides on High-Resistivity Silicon Substrates With Attenuation Constant Lower Than 1 dB/mm for Microwave and Millimeter-Wave Bands , 2011, IEEE Transactions on Electron Devices.