An Ultra Low Loss SerDes Signal Design on a FC Package Applied in 56 Gbps Networks

Recently, data transmission volumes of internet networks have grown explosively because most of consumer devices, such as smartphones, tablets, wearable devices, etc., all employ the same media. In the future, IoT will be applied to connect various devices related to human life. Thus, high data rate networking technology development becomes a very important task for Big Data transmission, which includes system transmission interface design. Inthis paper, the semiconductor package substrate design for 56 Gb/s high speed networking data transmission application is researched. For a design of 56 Gb/s using 30 mm trace length with differential signal via and 5+2+5 layers package structure on FCBGA, the optimization target for package substrate is 0.3 dB/mm differentialpair insertion loss at 28 GHz. The optimization design rules will be applied on real package product. Comparing with [1], our design concept has an obvious improvement of about 9dB.