Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading

Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation. These RBER variations would cause significantly diversed read latencies when reading data with traditional Low-Density Parity-Check (LDPC) codes designed for planar flash memories, which induces sub-optimal read performance of flash-based Solid-State Drives (SSDs). To investigate the latency diversity, this paper first performs a preliminary experiment and observes that LDPC read levels proportional to latencies increase in diverse speeds along with data retention. Then, by exploiting the observation results, a Multi-Granularity LDPC (MG-LDPC) read method is proposed to adapt level increase speed for each layer. Five LDPC engines with varied increase granularity are designed to adapt RBER speed requirements. Finally, two implementations for MG-LDPC are applied to assign LDPC engines for each flash layer in a fixed way or dynamically according to prior read levels. Experimental results show that the proposed two implementations can reduce SSD read response time by 21% and 47% on average, respectively.CCS CONCEPTS• Hardware→Temperature optimization; Network on chip; 3D integrated circuits.

[1]  Gregory R. Ganger,et al.  The DiskSim Simulation Environment Version 4.0 Reference Manual (CMU-PDL-08-101) , 1998 .

[2]  David J. C. MacKay,et al.  Good Error-Correcting Codes Based on Very Sparse Matrices , 1997, IEEE Trans. Inf. Theory.

[3]  Rina Panigrahy,et al.  Design Tradeoffs for SSD Performance , 2008, USENIX ATC.

[4]  Nanning Zheng,et al.  LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives , 2013, FAST.

[5]  Ren-Shuo Liu,et al.  EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  Fei Wu,et al.  REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance , 2016, 2016 32nd Symposium on Mass Storage Systems and Technologies (MSST).

[7]  Yuan-Hao Chang,et al.  Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  Tei-Wei Kuo,et al.  How to enable software isolation and boost system performance with sub-block erase over 3D flash memory , 2016, 2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[9]  Nanning Zheng,et al.  Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Rui Mao,et al.  P-Alloc , 2017, ACM Trans. Embed. Comput. Syst..

[11]  Hai Jin,et al.  LaLDPC: Latency-aware LDPC for Read Performance Improvement of Solid State Drives , 2017 .

[12]  Wei-Kuan Shih,et al.  Boosting the performance of 3D charge trap NAND flash with asymmetric feature process size characteristic , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Onur Mutlu,et al.  Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation , 2018, SIGMETRICS.

[14]  Liyan Qiao,et al.  A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory , 2018, Microprocess. Microsystems.

[15]  Il Han Park,et al.  A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory , 2018, IEEE Journal of Solid-State Circuits.