Real-Time Self Repairable Multiplexer for Fault Tolerant Systems

Using VLSI more number of transistors can be embedded on a single chip. As the space between transistors or circuits decreasing the system or chip is more susceptible to faults. Fault tolerant systems required to avoid inaccurate results. Multiplexer is a device which selects input signals based on select signal. The existing papers deal with only self checking multiplexer. In this paper a self repairing 2:1 multiplexer which can repair permanent and transient faults is proposed. Two different architectures are proposed for self repairing multiplexer. First architecture is having additional circuitry to repair the fault in multiplexer. In second architecture the building blocks of multiplexer like OR and AND gates itself are self repairable. These self repairing multiplexer architectures can detect and repair the single and multiple faults. The proposed architectures give 100% error recovery. The circuits are simulated using Cadence tool and verified the functionality.

[1]  Seyed Ghassem Miremadi,et al.  Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors , 2011, Microelectron. Reliab..

[2]  Sarada Musala,et al.  Fault Resistant 8-Bit Vedic Multiplier Using Repairable Logic , 2019, 2019 International Conference on Emerging Trends in Science and Engineering (ICESE).

[3]  Edward J. McCluskey,et al.  Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[4]  A. Majumdar,et al.  Fault Tolerant ALU System , 2012, 2012 International Conference on Computing Sciences.

[5]  Sarada Musala,et al.  Implementation of a full adder circuit with new full swing EX-OR/EX-NOR gate , 2013, 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

[6]  Jeong-A Lee,et al.  Self-repairing adder using fault localization , 2014, Microelectron. Reliab..

[7]  Avireni Srinivasulu,et al.  Self testing and fault secure XOR/XNOR circuit using FinFETs , 2016, 2016 International Conference on Communication and Signal Processing (ICCSP).

[8]  R. K. Sharma,et al.  Real-time fault tolerant full adder design for critical applications , 2016 .

[9]  Sudhakar M. Reddy,et al.  A Repair-for-Diagnosis Methodology for Logic Circuits , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Heinrich Theodor Vierhaus,et al.  On the Feasibility of Built-In Self Repair for Logic Circuits , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

[11]  Jack J. Dongarra,et al.  Self-healing network for scalable fault-tolerant runtime environments , 2010, Future Gener. Comput. Syst..

[12]  Niraj K. Jha,et al.  Design and synthesis of self-checking VLSI circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  James E. Smith,et al.  A Theory of Totally Self-Checking System Design , 1983, IEEE Transactions on Computers.

[14]  Ashish Jasuja,et al.  Real-time fault tolerant full adder using fault localization , 2018, 2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS).

[15]  Heinrich Theodor Vierhaus,et al.  Virtual TMR Schemes Combining Fault Tolerance and Self Repair , 2013, 2013 Euromicro Conference on Digital System Design.

[16]  Ka Lok Man,et al.  Concurrent Error Detection Adder Based on Two Paths Output Computation , 2011, 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications Workshops.

[17]  Parag K. Lala,et al.  Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.