Accurate and Ready-to-use Parasitic Capacitances Models for Advanced 2D/3D CMOS Device Structure Comparison

Introduction Parasitic capacitances become a performance constraint for ultrascaled technologies. In this work we present a unified solution to quickly evaluate capacitances on Bulk-Si, FDSOI, planar double gate (DG) [4] and FinFET [5] devices. Our model is accurate, ready-to-use for architecture comparison and easily adaptable for other structures such as QW transistors. In contrast to previous works on planar devices [1-3], gate-to-contact capacitance and corner capacitance are accurately modeled, quantum effects are taken into account thanks tabulated data, and inner fringe capacitance screening is physically implemented. Concerning FinFET, every parasitic components have been modeled. Finally, all models, including FINFET, have been validated by 2-3D numerical simulations and were used to evaluate parasitics impact following ITRS-roadmap requirement. Parasitic capacitances modeling on planar architecture In order to model capacitances for planar architecture (Fig 1), we use the classical parallel plate equations for Cgc, Cov, Cpcca and conformal mapping approach [6] for Cof, Cif, Cpccatop (capacitance between top of the gate and contact) and Ccorner (capacitance due to gate extension on STI) evaluation, which are composed of elliptical electric field lines. Conformal mapping consists in transforming the initial cartesian coordinate system (x,y) in an elliptical one (x’,y’) by applying the transformation function given in [7]: F x jy x' jy' where F arcos