Characterization and modelling of gate current injection in embedded non-volatile flash memory

Hot Carrier Injection (HCI) is investigated from the experimental and modelling perspectives. Extensive characterization of HCI is performed on flash devices to overcome the difficulties arising from direct gate injection measurements. Furthermore, a semi-analytical approach has been developped, capable of modelling both flash cell's electrostatics during transient operation and gate current under HCI by a non-local model valid for long and short channel devices.

[1]  Yusuf Leblebici,et al.  Analytical and compact models of the ONO capacitance in embedded non-volatile flash devices , 2009, ESSDERC 2009.

[2]  F. M. Bufler,et al.  Gate Current Calculations Using Spherical Harmonic Expansion of Boltzmann Equation , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[3]  Carla Golla,et al.  Flash Memories , 1999 .

[4]  Claudio Fiegna,et al.  Electron energy distributions in silicon structures at low applied voltages and high electric fields , 1996 .

[5]  Luca Larcher,et al.  Floating Gate Devices: Operation and Compact Modeling , 2004, Springer US.

[6]  A. Ghetti.  Hot-electron induced MOSFET gate current simulation by coupled silicon/oxide Monte Carlo device simulation , 2003 .

[7]  A. Ghetti.  Explanation for the temperature dependence of the gate current in metal-oxide-semiconductor transistors , 2002 .

[8]  S. Laux,et al.  Monte Carlo analysis of electron transport in small semiconductor devices including band-structure and space-charge effects. , 1988, Physical review. B, Condensed matter.

[9]  Y. Nissan-Cohen,et al.  A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistors , 1986, IEEE Electron Device Letters.

[10]  A. Tasch,et al.  A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's , 1996 .

[11]  L. Esaki,et al.  Tunneling in a finite superlattice , 1973 .

[12]  B. Eitan,et al.  Hot-electron injection into the oxide in n-channel MOS devices , 1981, IEEE Transactions on Electron Devices.

[13]  D. M. Kim,et al.  Stacked gate mid-channel injection flash EEPROM cell-Part II: analysis of gate current and modeling of programming characteristics , 1998 .

[14]  B. Riccò,et al.  Simple and efficient modeling of EPROM writing , 1991 .

[15]  R. K. Smith,et al.  Monte Carlo simulation of the CHISEL flash memory cell , 2000 .

[16]  Yusuf Leblebici,et al.  Embedded non–volatile memory study with surface potential based model , 2009 .

[17]  D. Esseni,et al.  The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and flash memory cells , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[18]  S. Laux,et al.  Understanding hot‐electron transport in silicon devices: Is there a shortcut? , 1995 .

[19]  L. Selmi,et al.  Injection efficiency of CHISEL gate currents in short MOS devices: physical mechanisms, device implications, and sensitivity to technological parameters , 2000 .

[20]  Yusuf Leblebici,et al.  Modeling study of capacitance and gate current in strained HighK-Metal gate technology , 2010 .

[21]  Kuniyoshi Yoshikawa,et al.  Degradation mechanism of flash EEPROM programming after program/erase cycles , 1993, Proceedings of IEEE International Electron Devices Meeting.

[22]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[23]  D. Rideau,et al.  Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).