Integration and system design trends of ADSL analog front ends and hybrid line interfaces

System optimization of the Analog Front End (AFE) and hybrid line interface is a key contributor in achieving high data rate and long reach for Asymmetric Digital Subscriber Line (ADSL) modems. Following a brief review of the ADSL system, the basic building blocks in an AFE, analog line interface, and hybrid matching issues are introduced. Integration trends of a single-channel AFE and circuit design challenges for multi-channel AFE are then presented. Line driver technologies and line receiver design issues are discussed with emphasis on the tradeoff between noise and linearity. Finally, design challenges for a highly integrated ADSL modem chipset with minimal external components are addressed.

[1]  R. Benton,et al.  A high-voltage line driver (HVLDR) for combined voice and data services , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[2]  H. Khorramabadi A CMOS line driver with 80-dB linearity for ISDN applications , 1992 .

[3]  Xiaomin Si,et al.  A CMOS analog front-end IC for DMT ADSL , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  K. Maclean,et al.  An ADSL central office analog front-end integrating actively-terminated line driver, receiver and filters , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  B. Nauta,et al.  Analog video line driver with adaptive impedance matching , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[6]  R. Mahadevan,et al.  A differential 160-MHz self-terminating adaptive CMOS line driver , 2000, IEEE Journal of Solid-State Circuits.

[7]  H. Casier,et al.  A 3.3 volt, low distortion ISDN line driver with a novel quiescent current control circuit , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[8]  C. Stacey,et al.  Mixed digital/analog signal processing for a single-chip 251Q U interface transceiver , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[9]  A. Wiesbauer,et al.  A 800 mW, full-rate ADSL-RT analog frontend IC with integrated line driver , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[10]  R. Koban,et al.  A broadband high-voltage SLIC for a splitter- and transformerless combined ADSL-Lite/POTS linecard , 2000, IEEE Journal of Solid-State Circuits.

[11]  M. Moyal,et al.  A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver , 1999 .

[12]  Walter Y. Chen,et al.  DSL: Simulation Techniques and Standards Development for Digital Subscriber Lines , 1998 .

[13]  N. Sooch,et al.  A CMOS direct access arrangement using digital capacitive isolation , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).