Design of 2.1 GHz CMOS Low Noise Amplifier

Abstract This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC 0.25 μ m CMOS process. Intended for use in 3 G , the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

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