Distributed thermal-aware task scheduling for 3D Network-on-Chip
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[1] Narayanan Vijaykrishnan,et al. Interconnect and thermal-aware floorplanning for 3D microprocessors , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[2] Mahmut T. Kandemir,et al. Thermal-aware task allocation and scheduling for embedded systems , 2005, Design, Automation and Test in Europe.
[3] Radu Marculescu,et al. Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[4] Partha Pratim Pande,et al. Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.
[5] Y.-K. Kwok,et al. Static scheduling algorithms for allocating directed task graphs to multiprocessors , 1999, CSUR.