Design of a low power Digital Down Converter for 802.16m - 4G WiMAX on FPGA
暂无分享,去创建一个
Sudhir Rao Rupanagudi | Varsha G. Bhat | G. HemalathaS. | N. Bhavana | M. Archana | V. ChandrikaB. | R. Ashwini | Keerti G. Torvi | R. DarshanS. | G. AbhilashB. | S. AnilK. | M. VinayakSwamyK.
[1] Mingqi Li,et al. Compensation method for the CIC filter in digital down converter , 2011, 2011 International Conference on Electrical and Control Engineering.
[2] Jingyu Hua,et al. A study of different matched filters in digital down converter , 2012, 2012 International Conference on Systems and Informatics (ICSAI2012).
[3] Ravi Kishore Kodali,et al. A factorization method for FPGA implementation of sample rate converter for a multi-standard radio communications , 2013, IEEE 2013 Tencon - Spring.
[4] Maria Theresa G. de Leon,et al. Active balun circuits for WiMAX receiver front-end , 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.
[5] Eugene B. Hogenauer. A class of digital filters for decimation and interpolation , 1980, ICASSP.
[6] Gai Peng Ao. The Basic Principle and FPGA Implementation of NCO , 2012, 2012 Second International Conference on Instrumentation, Measurement, Computer, Communication and Control.
[7] Zhiqiang Zhang,et al. Distributed arithmetic FIR filter for electrical resistance tomography system , 2011, 2011 Chinese Control and Decision Conference (CCDC).
[8] Hari Krishna Boyapati,et al. A comparison of DSP, ASIC, and RISC DSP based implementations of multiple access in LTE , 2010, 2010 4th International Symposium on Communications, Control and Signal Processing (ISCCSP).
[9] Qingxiang Zhang,et al. The Design of Digital Down Converter Based on FPGA , 2012, 2012 8th International Conference on Wireless Communications, Networking and Mobile Computing.
[10] Gerard J. M. Smit,et al. An optimal architecture for a DDC , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.
[11] Sudhir Rao Rupanagudi,et al. Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA , 2013 .
[12] S. R. Rupanagudi,et al. Novel high speed vedic mathematics multiplier using compressors , 2013, 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s).
[13] Saad Mahboob. FPGA implementation of digital up/down convertor for WCDMA system , 2010, 2010 The 12th International Conference on Advanced Communication Technology (ICACT).
[14] Jack E. Volder. The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..
[15] Ray Andraka,et al. A survey of CORDIC algorithms for FPGA based computers , 1998, FPGA '98.