HW / SW partitioning approach for reconfigurable system design

This paper presents a Genetic Algorithm (GA) based approach for Hardware/Software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to an AC-3 decoder function and its performance is compared with a greedy algorithm.

[1]  Niraj K. Jha,et al.  COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.

[2]  Carl Ebeling,et al.  Configurable computing: the catalyst for high-performance architectures , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[3]  P. Bjorn-Jorgensen,et al.  Critical path driven cosynthesis for heterogeneous target architectures , 1997, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97.

[4]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[5]  Guy Gogniat,et al.  Area time power estimation for FPGA based designs at a behavioral level , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[6]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).