CLOCK DYNAMIC LATCHES OPTIMIZATION.

The advantage of using single-phase clocked circuits in VLSI system design is well known. This class of circuits has the advantage of a simple clock distribution, low area for clock routing, reduced clock skew, and high speed. However, it is diffi- cult to choose the best configuration of such devices. Indeed, clear estimation criteria are needed to compare various kinds of latches. Moreover, to find the best sizes of the transistors in these latches, an automated procedure is needed. In this paper, a sim- ple compound criterion is proposed. This criterion is used in a proposed automated search procedure. That procedure is then applied to the split-output latch to obtain good configurations. The effect of imposing a stringent balance to the latch characte- ristics is also described. I. INTRODUCTION In the last few years, in order to increase the speed of mic~~~~tro~cs circuits, various kinds of true single-phase clocked dynamic latches were introduced (ll. These latches allow to simplify high speed clccking. However, hdmg the best latch configuration for a specific application is a difficult task. We already proposed a set of basic estimation criteria for analysis of such devices (21. However, these criteria are some- times contradictory. Thus, in this paper, we introduce a com- d performance measure and an algorithm, which automates the search of the best latch configuration, using this measure.