A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-/spl mu/m BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM's used as cache and control storages in mainframe computers.

[1]  Kunihiko Yamaguchi,et al.  High-speed sensing techniques for ultrahigh-speed SRAMs , 1992 .

[2]  Akio Takahashi,et al.  Hardware technology for Hitachi M-880 processor group , 1991, 1991 Proceedings 41st Electronic Components & Technology Conference.

[3]  Y. Ito,et al.  A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[4]  Youji Idei,et al.  A 1.5ns, 64kb ECL-CMOS SRAM , 1991, 1991 Symposium on VLSI Circuits.

[5]  Keiichi Higeta,et al.  A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[6]  Kunihiko Yamaguchi,et al.  An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM , 1989 .

[7]  Satoru Isomura,et al.  A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[8]  K. Nakamura,et al.  A 5 ns 1 Mb ECL BiCMOS SRAM , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[9]  S.E. Schuster,et al.  On-Chip Test Circuitry for a 2 ns Cycle 512Kb CMOS ECL SRAM , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[10]  J. Yamada,et al.  Fast-access BiCMOS SRAM architecture with a VSS generator , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[11]  Kenichi Ohhata,et al.  An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[12]  T. Ohsawa,et al.  A 60ns 4Mb CMOS DRAM with built-in self-test , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  Makoto Suzuki,et al.  A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[14]  F. Greene,et al.  Megabit bipolar LSI memory systems: IV , 1970 .

[15]  Rajiv V. Joshi,et al.  A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[16]  Yuen Chan,et al.  A 3ns 32K bipolar RAM , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[17]  B. Agusta.  A 64-bit planar double-diffused monolithic memory chip , 1969 .

[18]  Masanori Odaka,et al.  A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[19]  G. M. Lattimore,et al.  A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test , 1992 .

[20]  Koichiro Mashiko,et al.  A fully compensated active pull-down ECL circuit with self-adjusting driving capability , 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[21]  Joseph Ku,et al.  A 2.25 gbytes/s 1 Mbit smart cache SRAM , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[22]  Kunihiko Yamaguchi,et al.  A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM , 1992 .

[23]  Kunihiko Yamaguchi,et al.  A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[24]  W. K. Loh,et al.  A 1-Mbit CMOS dynamic RAM with design-for test functions , 1986 .