The 3-D Interconnect Technology Landscape

This overview article sheds light into the diverse notions and terms associated with 3-D circuits. It categorizes and classifies the various technologies/techniques and helps the experienced researcher as well as a newcomer to find an orientation in the complex 3-D landscape.

[1]  Mitsumasa Koyanagi,et al.  Future system-on-silicon LSI chips , 1998, IEEE Micro.

[2]  P. Ramm,et al.  InterChip via technology for vertical system integration , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[3]  E. Beyne.  Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[4]  Johan De Baets.  Technology for Embedding Active Dies , 2005 .

[5]  E. Beyne,et al.  The rise of the 3rd dimension for system intergration , 2006, 2006 International Interconnect Technology Conference.

[6]  Soonwook Hwang,et al.  A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  E. Beyne.  3D Integration Technologies at IMEC , 2008 .

[8]  M. Brunnbauer,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

[9]  J. Burghartz.  Ultra-thin Chip Technology and Applications , 2010 .

[10]  Eric Beyne.  Through-Silicon via Technology for 3D IC , 2011 .

[11]  G. Beyer,et al.  Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology , 2012, 2012 International Electron Devices Meeting.

[12]  P. Enquist,et al.  Scalable direct bond technology and applications driving adoption , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[13]  O. Faynot,et al.  3DVLSI with CoolCube process: An alternative path to scaling , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[14]  P. Wambacq,et al.  Vertical device architecture for 5nm and beyond: Device & circuit implications , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[15]  E. Beyne,et al.  Active-lite interposer for 2.5 & 3D integration , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[16]  G. Beyer,et al.  Advanced metallization scheme for 3×50µm via middle TSV and beyond , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[17]  E. Beyne.  Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[18]  G. Beyer,et al.  Small Pitch, High Aspect Ratio Via-Last TSV Module , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[19]  Pascal Vivet,et al.  Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits , 2016, IEEE Design & Test.

[20]  Eric Beyne,et al.  Reliability Challenges Related to TSV Integration and 3-D Stacking , 2016, IEEE Design & Test.

[21]  Matthias Petzold,et al.  Innovative Failure Analysis Techniques for 3-D Packaging Developments , 2016, IEEE Design & Test.

[22]  R. Huemoeller.  Embedded Die Packaging Technologies Enable Innovative 2 D and 3 D Structures for Portable Applications , .