On the interplay of loop caching, code compression, and cache configuration

Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%.

[1]  Ann Gordon-Ross,et al.  Lightweight runtime control flow analysis for adaptive loop caching , 2010, GLSVLSI '10.

[2]  Bill Moyer,et al.  A low power unified cache architecture providing power and performance flexibility , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[3]  Jörg Henkel,et al.  Code compression for low power embedded system design , 2000, Proceedings 37th Design Automation Conference.

[4]  Nikil D. Dutt,et al.  Automatic tuning of two-level caches to embedded applications , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Luca Benini,et al.  Cached-code compression for energy minimization in embedded processors , 2001, ISLPED '01.

[6]  André C. Nácul,et al.  Dynamic voltage and cache reconfiguration for low power , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  David H. Albonesi,et al.  Selective cache ways: on-demand cache resource allocation , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[8]  David A. Huffman,et al.  A method for the construction of minimum-redundancy codes , 1952, Proceedings of the IRE.

[9]  Frank Vahid,et al.  A highly configurable cache architecture for embedded systems , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[10]  Andrew Wolfe,et al.  Executing compressed programs on an embedded RISC architecture , 1992, MICRO.

[11]  Frank Vahid,et al.  Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example , 2002, IEEE Computer Architecture Letters.

[12]  Nikil D. Dutt,et al.  A first look at the interplay of code reordering and configurable caches , 2005, GLSVLSI '05.

[13]  Frank Vahid,et al.  A self-tuning cache architecture for embedded systems , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[14]  Frank Vahid,et al.  A self-tuning cache architecture for embedded systems , 2004 .

[15]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[16]  Frank Vahid,et al.  A One-Shot Configurable-Cache Tuner for Improved Energy and Performance , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[17]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .