Low power optimization of instruction cache based on tag check reduction

In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on nearly every clock cycle. This paper proposes a low power optimization method of instruction cache based on tag check reduction. By using the compiler to denote the loops whose length is less than the instruction cache size and adding some simple logic circuits to control the tag array access, the unnecessary tag checks could be reduced and the instruction cache energy consumption could be saved. Experimental results of the SuperV DSP show that this approach could save 20.1% of instruction cache power consumption, with only 0.69% of area increasing and 0.05% of performance degradation.