A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs that are using Table-based routing. The proposed approach encompasses TPG and TRA located in the Network Adapter (NA) as well as a Packet Comparing Module (PCM) embedded in the routers. The approach, in addition, with a high scalability leads to 100% Test Coverage (TC) and 82.3% capability of diagnosing faulty channels in NoCs with a high scale. Furthermore, the approach is capable of being performed within one Round (two phase) run with a total time of 70 clocks which is considered as cost-effective compared with the preceding methods. The simulation results demonstrate that the hardware cost of PCM is trivial compared with the hardware of RASoC, HERMES, Æthereal and Vici routers.

[1]  David Blaauw,et al.  Vicis: A reliable network for unreliable silicon , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[2]  Chen Xin,et al.  Novel Core Test Wrapper Design Supporting Multi-mode Testing of NoC-based SoC , 2013 .

[3]  Altamiro Amadeu Susin,et al.  RASoC: a router soft-core for networks-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Marcelo Lubaszewski,et al.  Concurrent test of Network-on-Chip interconnects and routers , 2010, 2010 11th Latin American Test Workshop.

[6]  Raimund Ubar,et al.  Testing Strategies for Networks on Chip , 2003, Networks on Chip.

[7]  Ali Sadeghi,et al.  A Novel HW/SW Based NoC Router Self-Testing Methodology , 2016 .

[8]  Sungho Kang,et al.  A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System , 2014, 2014 IEEE 23rd Asian Test Symposium.

[9]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[10]  Marcelo Lubaszewski,et al.  Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[11]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[12]  Coniferous softwood.  GENERAL TERMS , 2003 .

[13]  Guangming Chen.  SPAcENoCs : A Scalable Platform for FPGA Accelerated Emulator of NoCs , 2013 .

[14]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[15]  Armin Alaghi,et al.  Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[16]  Alexandre M. Amory,et al.  Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism , 2007, IET Comput. Digit. Tech..

[17]  Diana Adler.  Delay Fault Testing For Vlsi Circuits , 2016 .

[18]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[19]  Babak Aghaei,et al.  The new test wrapper design for core testing in packet-switched micro-network on chip , 2009, 2009 2nd International Conference on Power Electronics and Intelligent Transportation System (PEITS).

[20]  Alexandre M. Amory,et al.  A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..

[21]  G. Nazarian,et al.  On-line testing of routers in networks-on-chip , 2008 .

[22]  Santosh Biswas,et al.  An odd-even model for diagnosis of shorts on NoC interconnects , 2015, 2015 Annual IEEE India Conference (INDICON).

[23]  Javad Alirezaie,et al.  A novel test strategy and fault-tolerant routing algorithm for NoC routers , 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

[24]  Kwang-Ting Cheng,et al.  Delay fault testing for VLSI circuits , 1998 .

[25]  Melvin A. Breuer,et al.  MAXIMAL DIAGNOSIS FOR WIRING NETWORKS , 1991, 1991, Proceedings. International Test Conference.

[26]  Michele Favalli,et al.  Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture , 2011, 2011 Design, Automation & Test in Europe.

[27]  Santosh Biswas,et al.  Impact of NoC interconnect shorts on performance metrics , 2016, 2016 Twenty Second National Conference on Communication (NCC).

[28]  Ahmad Khademzadeh,et al.  Online-Structural Testing of Routers in Network on Chip , 2011 .

[29]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[30]  Jong-Sun Kim,et al.  On-chip network based embedded core testing , 2004, IEEE International SOC Conference, 2004. Proceedings..

[31]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.

[32]  Partha Pratim Pande,et al.  BIST for network-on-chip interconnect infrastructures , 2006, 24th IEEE VLSI Test Symposium.

[33]  Dong Xiang,et al.  A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing , 2016, TODE.

[34]  Marcelo Lubaszewski,et al.  Test and Diagnosis of Routers , 2012 .

[35]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[36]  Luigi Carro,et al.  A study on communication issues for systems-on-chip , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[37]  Charles E. Stroud.  A Designer's Guide to Built-In Self-Test , 2002 .

[38]  Luca Benini,et al.  A distributed and topology-agnostic approach for on-line NoC testing , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[39]  Luca Benini,et al.  At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs , 2014, IEEE Transactions on Computers.

[40]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[41]  Ye Zhang,et al.  Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[43]  Ahmad Khademzadeh,et al.  Link Testing: a Survey of Current Trends in Network on Chip , 2017, Journal of Electronic Testing.

[44]  S. Kumar,et al.  Design issues and performance evaluation of mesh NoC with regions , 2005, 2005 NORCHIP.

[45]  Allen C. Cheng.  Comprehensive Study on Designing Memory BIST : Algorithms , Implementations and Trade-offs By : , 2002 .

[46]  Santosh Biswas,et al.  An on-line test solution for addressing interconnect shorts in on-chip networks , 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

[47]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[48]  Ravi Shankar,et al.  Survey of Network on Chip (NoC) Architectures & Contributions , 2009 .

[49]  Zainalabedin Navabi,et al.  Using the Inter- and Intra-Switch Regularity in NoC Switch Testing , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[50]  Johnny Öberg,et al.  Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[51]  Hideo Fujiwara,et al.  Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip , 2016, IEEE Transactions on Computers.

[52]  Alexandre M. Amory,et al.  A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip , 2008, IEEE Transactions on Computers.

[53]  Marcelo Lubaszewski,et al.  Diagnosis of interconnect shorts in mesh NoCs , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[54]  Kwang-Ting Cheng,et al.  Comprehensive online defect diagnosis in on-chip networks , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).