The SNAP project: towards sub-nanosecond arithmetic
暂无分享,去创建一个
[1] G. De Micheli,et al. Approaching a nanosecond: a 32 bit adder , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[2] Gary Wayne Bewick. Fast Multiplication: Algorithms and Implementations , 1994 .
[3] Michael J. Flynn,et al. An improved algorithm for high-speed floating-point addition , 1990 .
[4] Michael J. Flynn,et al. A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency , 1992 .
[5] Michael J. Flynn,et al. Binary multiplication Using Partially Redundant Multiples , 1992 .
[6] Paul Michael Farmwald,et al. On the design of high performance digital arithmetic units , 1981 .
[7] E. F. Klass. Wave pipelining : Theoretical and practical issues in CMOS , 1994 .
[8] Huey Ling. High Speed Binary Adder , 1981, IBM J. Res. Dev..
[9] Giovanni De Micheli,et al. Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Michael J. Flynn,et al. Design And Implementation Of The Snap Floating-Point Adder , 1991 .
[11] Giovanni De Micheli,et al. Inserting active delay elements to achieve wave pipelining , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[12] Michael J. Flynn,et al. High-Speed Addition in CMOS , 1992, IEEE Trans. Computers.
[13] Michael J. Flynn,et al. Implementing Division and Other Floating-Point Operations: A System Perspective , 1995 .
[14] Eric M. Schwarz. High-radix algorithms for high-order arithmetic operations , 1993 .
[15] Michael J. Flynn,et al. Reducing division latency with reciprocal caches , 1996, Reliab. Comput..
[16] Michael J. Flynn,et al. An Analysis of Division Algorithms and Implementations , 1995 .
[17] Kevin J. Nowka,et al. Environmental Limits on the Performance of CMOS Wave-Pipelined Circuits , 1994 .
[18] Michael J. Flynn,et al. Fast Division Using Accurate Quotient Approximations to Reduce the Number of Iterations , 1992, IEEE Trans. Computers.
[19] Michael J. Flynn,et al. A Variable Latency Pipelined Floating-Point Adder , 1996, Euro-Par, Vol. II.
[20] S. Simon Wong,et al. Membrane multichip module technology on silicon , 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.
[21] DAVID M. MANDELBAUM,et al. A method for calculation of the square root using combinatorial logic , 1993, J. VLSI Signal Process..
[22] Fabian Klass. Balancing Circuits For Wave Pipelining , 1992 .
[23] G. De Micheli,et al. Circuit and architecture trade-offs for high-speed multiplication , 1991 .
[24] Nhon T. Quach,et al. Reducing The Latency Of Floating-Point Arithmetic Operations , 1993 .
[25] Renato Stefanelli,et al. A Suggestion for a High-Speed Parallel Binary Divider , 1972, IEEE Transactions on Computers.
[26] Michael J. Flynn,et al. Architecture Evaluator''s Work Bench and its Application to Microprocessor Floating Point Units , 1995 .
[27] Derek Chi-Lan Wong. Techniques for designing high-performance digital circuits using wave pipelining , 1992 .
[28] Michael J. Flynn,et al. Design Issues in Division and Other Floating-Point Operations , 1997, IEEE Trans. Computers.