Development of an LFSR based test pattern generator for functional logic testing

This paper presents the development of an LFSR based test pattern generator (TPG) to test the functional logic of combinational and sequential circuits. Primitive polynomial based LFSRs and deterministic testing algorithms are applied simultaneously on the circuit under test (CUT) to detect the fault with minimum test length. Fault simulation was performed on ISCAS'85 and ISCAS'89 benchmark circuits using digital fault simulators FSIM and Tetramax. The proposed technique achieved complete fault coverage with shorter test sequences and required less hardware for its implementation.

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