Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

[1]  Yusuke Shuto,et al.  Energy performance of nonvolatile power-gating SRAM using SOTB technology , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[2]  Joseph Y.-T. Leung,et al.  Handbook of Real-Time and Embedded Systems , 2007 .

[3]  Hideharu Amano,et al.  Switching region analysis for SOTB technology , 2017, 2017 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

[4]  Wolfgang Rosenstiel,et al.  Leveraging FDSOI through body bias domain partitioning and bias search , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Kazutoshi Kobayashi,et al.  Impact of body bias on soft error tolerance of bulk and Silicon on Thin BOX structure in 65-nm process , 2014, 2014 IEEE International Reliability Physics Symposium.

[6]  Daisuke Sasaki,et al.  3D NoC with Inductive-Coupling Links for Building-Block SiPs , 2014, IEEE Transactions on Computers.

[7]  Y. Kojima,et al.  Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[8]  Hideharu Amano,et al.  An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET , 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[9]  Narayanan Vijaykrishnan,et al.  Evaluating run-time techniques for leakage power reduction , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[10]  Pradip Bose,et al.  Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[11]  Nobuyuki Yamasaki,et al.  Analysis of Body Bias Control for Real Time Systems , 2016 .

[12]  Niraj K. Jha,et al.  Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Narayanan Vijaykrishnan,et al.  Characterization and modeling of run-time techniques for leakage power reduction , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  T. Ghani,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[15]  Amano Hideharu,et al.  Power optimization of micro-controller with Sillicon on Thin Buried Oxide , 2013 .

[16]  Hiroshi Nakamura,et al.  Design and evaluation of fine-grained power-gating for embedded microprocessors , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  Pascal Benoit,et al.  Power management through DVFS and dynamic body biasing in FD-SOI circuits , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  P. E. Allen,et al.  Body-driving as a low-voltage analog design technique for CMOS technology , 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).