Systolic-Type Arrays for Matrix Algorithms

In this chapter, we describe an architectural model of processor arrays for matrix algorithms, including the different types of cells that can be used in such arrays. We refer to these architectures as “systolic-type” arrays because they use some of the features originally proposed for systolic structures [Kun82]. We first describe the issues arising during the process of implementing matrix algorithms as application-specific arrays, and summarize the design space as well as performance and cost measures for these computing structures. We also present the models of computation suitable for systolic-type arrays, and discuss the relationship among the size of matrices and arrays. Based on the concepts described here, the following chapters will present a method to implement matrix algorithms in systolic-type arrays.