CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET With $I_{ON}=156~\mu \text{A}/\mu \text{m}$ at $V_{DD}= 0.5$ V and

We report CMOS-compatible n-channel InGaAson-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiN<sub>x</sub> spacers, a scaled high-k/metal gate (capacitance equivalent thickness of ~1.5 nm), raised source and drain doped to ~6 × 10<sup>19</sup>/cm<sup>3</sup>, and fin width scaled down to 15 nm. Very good control of short-channel effects is demonstrated down to a gate length of 50 nm with a minimum subthreshold swing of 92 mV/decade at V<sub>DS</sub> = 0.5 V and a drain-induced barrier lowering of 57 mV/V. An ON-state current (I<sub>ON</sub>) of 156 μA/μm is also reported for a supply voltage of 0.5 V and a fixed OFF-state current of 100 nA/μm. This I<sub>ON</sub> value is the highest reported to date for CMOS-compatible InGaAs devices integrated on Si.

[1]  P. Hurley,et al.  Junctionless InGaAs MOSFETs with InAlAs barrier isolation and channel thinning by digital wet etching , 2013, 71st Device Research Conference.

[2]  Peide D. Ye,et al.  Size-Dependent-Transport Study of In 0 . 53 Ga 0 . 47 As Gate-All-Around Nanowire MOSFETs : Impact of Quantum Confinement and Volume Inversion , 2012 .

[3]  Kelin J. Kuhn.  CMOS scaling beyond 32nm: Challenges and opportunities , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[4]  P. Hurley,et al.  An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors , 2013 .

[5]  G. Dewey,et al.  Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[6]  Jean Fompeyrine,et al.  Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon , 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[7]  C. Merckling,et al.  An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[8]  Heike Riel,et al.  Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si , 2015 .

[9]  Peide D. Ye,et al.  Size-Dependent-Transport Study of $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion , 2012, IEEE Electron Device Letters.

[10]  V. Djara,et al.  Low Dit HfO2/Al2O3/In0.53Ga0.47As gate stack achieved with plasma-enhanced atomic layer deposition , 2015 .

[11]  E. Leobandung,et al.  Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution , 2013, 2013 IEEE International Electron Devices Meeting.

[12]  V. Djara,et al.  Tri-gate InGaAs-OI junctionless FETs with PE-ALD Al2O3 gate dielectric and H2/Ar anneal , 2016 .

[13]  S. Takagi,et al.  Strained extremely-thin body In0.53Ga0.47As-on-insulator MOSFETs on Si substrates , 2013, 2013 Symposium on VLSI Technology.

[14]  Isabelle Ferain,et al.  Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors , 2011, Nature.

[15]  M. Carroll,et al.  Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping , 2007 .

[16]  Niamh Waldron,et al.  InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates , 2014, IEEE Electron Device Letters.

[17]  M. Rodwell,et al.  Ultrathin InAs-channel MOSFETs on Si substrates , 2015, International Symposium on VLSI Technology, Systems, and Applications.

[18]  D. Caimi,et al.  Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[19]  P. D. Kirsch,et al.  Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications , 2013, 2013 IEEE International Electron Devices Meeting.

[20]  M. J. W. Rodwell,et al.  Record Ion (0.50 mA/µm at VDD = 0.5 V and Ioff = 100 nA/µm) 25 nm-gate-length ZrO2/InAs/InAlAs MOSFETs , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[21]  D. Caimi,et al.  An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[22]  K. Cheng,et al.  Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates , 2013, 2013 IEEE International Electron Devices Meeting.

[23]  High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V , 2014, 2014 IEEE International Electron Devices Meeting.

[24]  J. D. del Alamo.  Nanometre-scale electronics with III-V compound semiconductors. , 2011, Nature.

[25]  P. Hashemi,et al.  Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).