A BiCMOS receive/transmit PLL pair for serial data communication

DATA Phase-locked loops for frequency synthesis and clock recovery in serial data communication have I I been designed and fabricated. A master-slave loop architecture uses the frequency reference for the transmit loop to set the center frequency of the receive loop. These circuits are fabricated in a 1.2 pm BiCMOS process and consume 750 7izW from a single 5 volt supply. BiCMOS circuit design allows operation speeds of up to 300 MHz and compatibility with a high level of system integration.

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