Fast and accurate workload-level neural network based IC energy consumption estimation

A fast, yet accurate nanoscale IC energy estimation is a design-time desideratum for area-delay-power-reliability optimized circuits and architectures. This paper introduces an IC energy estimation approach, which instead of sequentially propagating workload vectors throughout the circuit, relies on an one time propagation of the workload statistics. To this end, the basic gates need be SPICE pre-characterized with respect to (w.r.t.) static and dynamic energy consumption per input transition type and Neural Network based gate models constructed and trained in order to estimate gate output statistics and consumed energy based on gate input statistics, i.e., the ‘0’ → ‘0’, ‘0’ → ‘1’, ‘1’ → ‘0’, and ‘1’ → ‘1’ transition probabilities. Both pre-characterization and training are done once per technology node and do not contribute to the actual evaluation time. In this way, regardless of n, the number of workload input vectors, by propagating signal statistics instead of logic values the overall circuit energy consumption is evaluated in one instead of n circuit traversals. Moreover, as opposed to the constant and equal gate delay assumption utilized in state of the art energy estimation methods, the proposed approach takes into account the real gate propagation delays, which yields estimates that are closer to the actual energy figures. We evaluated with the proposed method the static and dynamic energy consumption for a set of ISCAS'85 circuits and a 10, 508-gate hashing circuit, using TSMC 40nm CMOS technology, and 50, 000-vector workloads. The experiments indicate that our method provides an estimation error below 2.6% and 1.5% for dynamic and static energy, respectively, when compared to the accurate SPICE measurements, while providing an estimation speedup in the order of 50, 000x.