IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

Abstract A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.

[1]  Krishnendu Chakrabarty,et al.  Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[3]  Rajesh K. Gupta,et al.  Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[4]  Bishop Brock,et al.  A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling , 2002, IEEE J. Solid State Circuits.

[5]  Dennis Sylvester,et al.  Pushing ASIC performance in a power envelope , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  E.J. Marinissen,et al.  Scan chain design for test time reduction in core-based ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Tianzhou Chen,et al.  Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors , 2008, 2008 International Conference on Embedded Software and Systems.

[8]  Joonwon Lee,et al.  Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors , 2008, IEEE Transactions on Parallel and Distributed Systems.

[9]  John M. Cohn,et al.  Managing power and performance for System-on-Chip designs using Voltage Islands , 2002, ICCAD 2002.

[10]  Edward J. McCluskey,et al.  Detecting delay flaws by very-low-voltage testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  Krishnendu Chakrabarty,et al.  Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints , 2002, Proceedings. International Test Conference.

[12]  José M. Solana Reducing test application time, test data volume and test power through Virtual Chain Partition , 2009, Integr..

[13]  Ishak Aris,et al.  Challenges and directions for testing IC , 2004, Integr..

[14]  Petru Eles,et al.  Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns , 2008, 2008 Design, Automation and Test in Europe.

[15]  Mark Zwolinski,et al.  Dynamic Voltage Scaling Aware Delay Fault Testing , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[16]  Rohit Kapur,et al.  CTL the language for describing core-based test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[17]  Mats Brorsson,et al.  An adaptive chip-multiprocessor architecture for future mobile terminals , 2002, CASES '02.

[18]  Krishnendu Chakrabarty,et al.  Time-Division Multiplexing for Testing DVFS-Based SoCs , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Krishnendu Chakrabarty,et al.  Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..

[21]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[22]  Leon Stok,et al.  Minimizing power with flexible voltage islands , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[23]  Yinshui Xia,et al.  Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence , 2016, Integr..

[24]  Nilanjan Mukherjee,et al.  Resource allocation and test scheduling for concurrent test of core-based SOC design , 2001, Proceedings 10th Asian Test Symposium.

[25]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[26]  G. Magklis,et al.  Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor , 2003, IEEE Micro.

[27]  Wan Yeon Lee,et al.  Energy-Efficient Scheduling of Periodic Real-Time Tasks on Lightly Loaded Multicore Processors , 2012, IEEE Transactions on Parallel and Distributed Systems.

[28]  Resve A. Saleh,et al.  Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip , 2007, Integr..

[29]  Krishnendu Chakrabarty,et al.  Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands , 2011, 2011 Asian Test Symposium.

[30]  Masanori Hashimoto,et al.  A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations , 2013, Integr..

[31]  Yervant Zorian,et al.  On IEEE P1500's Standard for Embedded Core Test , 2002, J. Electron. Test..

[32]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[33]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).