A 2.7 V CMOS IF transceiver for PHS application

This paper describes a single chip 2.7 V 248.5 MHz IF transceiver including VCO, PLL and a complete voice codec for personal handy phone system (PHS). The IC is implemented in a 0.6-/spl mu/m CMOS process. It achieves a receive sensitivity of -86 dBV, 1 dB compression point of -9 dBV and 32 dB image rejection. This circuit consumes 24 mA in the receive mode, 26 mA in the transmit mode, and 4.5 mA in the voice codec.

[1]  A. Hairapetian,et al.  An 81 MHz IF receiver in CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.