Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization

To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process

[1]  D. Edelstein,et al.  Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

[2]  J. Yoshioka,et al.  Eutectic Sn-Ag solder bump process for ULSI flip chip technology , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[3]  P. Andry,et al.  Characterization of micro-bump C4 interconnects for Si-carrier SOP applications , 2006, 56th Electronic Components and Technology Conference 2006.

[4]  Paul S. Andry,et al.  Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[5]  H. Ezawa,et al.  Pb-free bumping by alloying electroplated metal stacks , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[6]  D. Frear,et al.  Lead-free flip chip interconnect reliability for DCA and FC-PBGA packages , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[7]  Keith A. Jenkins,et al.  Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..

[8]  Karl J. Puttlitz,et al.  Area array interconnection handbook , 2001 .

[9]  L. F. Miller,et al.  Controlled collapse reflow chip joining , 2000, IBM J. Res. Dev..