An Algorithm and Architecture of VLD for AVS HDTV Application

This paper presents a novel VLD decoder for AVS.It finishes Exp-Golomb code decoding,looking up table,calculating symbols and updating table in one cycle,it uses combinational logic looking up table to avoids memory access and decreases area greatly,it uses pipeline technique to improve performance.Simulate this module and implement use 0.18μm,the frequency reaches 176MHz and the circuit costs 8k Gates.