The integration nf 2-D optoelectronic interfaces with silicon chips, employing what is known ab smart-pirel technology, can overcome many of the foreseen limitations of conventional interconnects [I]. The solution is to provide free-space optical interconnects operating at thc silicon on-chip clock-ralc and with the numbers required to yield the necessary aggregate bandwidth. T o investigate the application of this approach to parallel information processing we have been building an oploeiectronic data sorting machine as a system dcmunstrator. 'The architecture of the optoelectronic sorter and the dcsign of the cumponenls was described previously (2).