Markov chains and probabilistic computation-a general framework for multiplexed nanoelectronic systems

In emerging nanotechnologies, reliable computation will have to be carried out with unreliable components being integral parts of computing systems. One promising scheme for designing these systems is von Neumann's multiplexing technique. Using bifurcation theory and its associated geometrical representation, we have studied a NAND-multiplexing system recently proposed. The behavior of the system is characterized by the stationary distribution of a Markov chain, which is uni- or bi-modal, when the error probability of NAND gates is larger or smaller than the threshold value, respectively. The two modes and the median of the stationary distribution are the keys to the characterization of the system reliability. Examples of potential future nanochips are used to illustrate how the NAND-multiplexing technique can lead to high system reliability in spite of large gate error probability while keeping the cost of redundancy moderate. In nanoelectronic systems, while permanent defects can be taken care of by reconfiguration, probabilistic computation schemes can incorporate another level of redundancy so that high tolerance of transient errors may be achieved. The Markov chain model is shown to be a powerful tool for the analysis of multiplexed nanoelectronic systems.

[1]  Peter M. Kogge,et al.  A Potentially Implementable FPGA for Quantum-Dot Cellular Automata , 2002 .

[2]  A. S. Sadek,et al.  Parallel information and computation with restitution for noise-tolerant nanoscale logic networks , 2003 .

[3]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, ISCA 2001.

[4]  Nicholas Pippenger,et al.  Reliable computation by formulas in the presence of noise , 1988, IEEE Trans. Inf. Theory.

[5]  J. Meindl,et al.  Limits on silicon nanoelectronics for terascale integration. , 2001, Science.

[6]  C. Dekker,et al.  Logic Circuits with Carbon Nanotube Transistors , 2001, Science.

[7]  Rüdiger Reischuk.  Can large fanin circuits perform reliable computations in the presence of faults? , 2000, Theor. Comput. Sci..

[8]  M. Forshaw,et al.  Architectures for reliable computing with unreliable nanodevices , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[9]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[10]  Steven H. Strogatz,et al.  Nonlinear Dynamics and Chaos , 2024 .

[11]  Snider,et al.  Digital logic gate using quantum-Dot cellular automata , 1999, Science.

[12]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[13]  Jie Han,et al.  A system architecture solution for unreliable nanoelectronic devices , 2002 .

[14]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[15]  A. S. Sadek,et al.  Fault-tolerant techniques for nanocomputers , 2002 .

[16]  L. Breuer.  Introduction to Stochastic Processes , 2022, Statistical Methods for Climate Scientists.

[17]  Sandeep K. Shukla,et al.  Evaluating the reliability of defect-tolerant architectures for nanotechnology with probabilistic model checking , 2004, 17th International Conference on VLSI Design. Proceedings..

[18]  William S. Evans,et al.  On the Maximum Tolerable Noise for Reliable Computation by Formulas , 1998, IEEE Trans. Inf. Theory.

[19]  P. Jonker,et al.  A defect-?and fault-tolerant architecture for nanocomputers , 2003 .

[20]  A. DeHon.  Array-Based Architecture for Molecular Electronics , 2001 .

[21]  Jie Han,et al.  A Fault-Tolerant Technique for Nanocomputers : NAND Multiplexing , 2002 .

[22]  L. Schulman,et al.  Information theory and noisy computation , 1995, Proceedings of 1995 IEEE International Symposium on Information Theory.