Concurrent Multiresource Arbiter: Design and Applications

This paper presents a novel type of asynchronous arbiter that allocates M interchangeable resources among N clients. This arbiter enables the concurrent utilization of multiple resources and is a useful device in various load-balancing circuits. Dedicated request signals from the resources and the clients are used in pairs to form each new grant. The 2 × 2 arbiter is examined as an accessible special case of the N × M arbiter. A concurrent implementation is compared to fully sequential design. It is shown that the sequential design can be more practical when the time between a grant and the withdrawal of the initial request is small. The concurrent design provides higher performance in a system with a longer resource utilization time. A scalable tiled structure is developed to extend the arbiter structure beyond 2 × 2 to support N clients and M resources. Models and subsequent implementations of the tiles are presented. The tiles can be repeated without the use of additional connecting logic, enabling the construction of arbiters of larger sizes. Several examples demonstrate the usage of the arbiter.

[1]  K. Mani Chandy,et al.  Parallel program design - a foundation , 1988 .

[2]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[3]  Alexandre Yakovlev,et al.  Priority arbiters , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[4]  Kees van Berkel,et al.  Scalable Multi-Input-Multi-Output Queues With Application to Variation-Tolerant Architectures , 2009, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Mark R. Greenstreet,et al.  An event spacing experiment , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[6]  Alexandre Yakovlev,et al.  The Magic Rule of Tiles: Virtual Delay Insensitivity , 2009, PATMOS.

[7]  Wei Song,et al.  Improving the Throughput of Asynchronous On-chip Networks with SDM , 2010 .

[8]  D. J. Kinniment.  Synchronization and Arbitration in Digital Systems , 2008 .

[9]  John P. Hayes,et al.  Multiple Bus Architectures , 1987, Computer.

[10]  Yuval Tamir,et al.  Symmetric Crossbar Arbiters for VLSI Communication Switches , 1993, IEEE Trans. Parallel Distributed Syst..

[11]  Victor Khomenko,et al.  Model checking based on prefixes of petri net unfoldings , 2003 .

[12]  Warren D. Little,et al.  Asynchronous Arbiter Module , 1975, IEEE Transactions on Computers.

[13]  Jens Sparsø,et al.  Asynchronous circuit design - A tutorial , 2001 .

[14]  Fabien Clermidy,et al.  A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip , 2008, IEEE Journal of Solid-State Circuits.

[15]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[16]  Alexandre Yakovlev,et al.  Workcraft - A Framework for Interpreted Graph Models , 2009, Petri Nets.

[17]  Andrew Lines,et al.  Asynchronous interconnect for synchronous SoC design , 2004, IEEE Micro.

[18]  Igor Benko,et al.  Delay-insensitive solutions to the committee problem , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[19]  C. van Berkel,et al.  Beware the three-way arbiter , 1999 .