GORDIAN: VLSI placement by quadratic programming and slicing optimization

The authors present a placement method for cell-based layout styles. It is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization. Methods using the divide-and-conquer paradigm usually lose the global view by generating smaller and smaller subproblems. In contrast, GORDIAN maintains the simultaneous treatment of all cells over all global optimization steps, thereby considering constraints that reflect the current dissection of the circuit. The global optimizations are performed by solving quadratic programming problems that possess unique global minima. Improved partitioning schemes for the stepwise refinement of the placement are introduced. The area utilization is optimized by an exhaustive slicing procedure. The placement method is applied to real-world problems, and excellent results in terms of placement quality and computation time are obtained. >

[1]  G. Kedem,et al.  An algorithm for quadrisection and its application to standard cell placement , 1988 .

[2]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[3]  Antoni A. Szepieniec,et al.  The Genealogical Approach to the Layout Problem , 1980, 17th Design Automation Conference.

[4]  M. Hestenes,et al.  Methods of conjugate gradients for solving linear systems , 1952 .

[5]  Chung-Kuan Cheng,et al.  Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  John P. Blanks.  Near-Optimal Placement Using a Quadratic Objective Function , 1985, 22nd ACM/IEEE Design Automation Conference.

[7]  A. Weller,et al.  An ADVANCELL 1.0 mainframe chipset-2.2 million transistors on 11 ICs , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[8]  D. A. Mlynski,et al.  A Combined Force and Cut Algorithm for Hierarchical VLSI Layout , 1982, DAC 1982.

[9]  Frank M. Johannes,et al.  On the Relative Placement and the Transportation Problem for Standard-Cell Layout , 1986, 23rd ACM/IEEE Design Automation Conference.

[10]  G. J. Wipfler,et al.  A Combined Force and Cut Algorithm for Hierarchical VLSI Layout , 1982, 19th Design Automation Conference.

[11]  Christian Müller-Schloer,et al.  Design of VLSI circuits - based on Venus , 1987 .

[12]  Larry J. Stockmeyer,et al.  Optimal Orientations of Cells in Slicing Floorplan Designs , 1984, Inf. Control..

[13]  R.T.A. Howell.  Computer-Aided Design of Electronic Circuits , 1968 .

[14]  Stephen W. Director,et al.  Mason: A Global Floorplanning Approach for VLSI Design , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Ralph H. J. M. Otten,et al.  Optimal slicing of plane point placements , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[16]  R. H. J. M. Otten,et al.  Graphs in floor‐plan design , 1988 .

[17]  G. Sigl,et al.  GORDIAN: a new global optimization/rectangle dissection method for cell placement , 1988, ICCAD 1988.

[18]  Brian W. Kernighan,et al.  A Procedure for Placement of Standard-Cell VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Georg Sigl,et al.  GORDIAN: a new global optimization/rectangle dissection method for cell placement , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[20]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[21]  Gerhard Zimmerman,et al.  A new area and shape function estimation technique for VLSI layouts , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[22]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[23]  Ernest S. Kuh,et al.  Proud: a fast sea-of-gates placement algorithm , 1988, DAC '88.

[24]  Philip E. Gill,et al.  Practical optimization , 1981 .

[25]  Christian Müller-Schloer,et al.  Design of VLSI Circuits , 1987 .