Development of numerical modeling approach on substrate warpage prediction

Prediction and reduction of substrate warpage is very important to enhance assembly yield, and to improve reliability in the microelectronic packaging industry. Modeling the copper trace pattern of a packaging substrate is a difficult and time consuming task. Modeling of these patterns are often too complex for FEM to model exactly, so steps are taken to reduce the number of elements and computation time necessary to model trace patterns with FEM. An often used approach is to use micromechanics considerations to find effective material properties for layers of mixed copper and dielectric material. This approach yields isotropic properties for trace pattern layers based on the percentages of copper and dielectric material present in that layer. But that method is not so accurate to use it always. So, a new approach based on copper percentage at each sub region of a metal layer is proposed. It is found that Cu distribution has a major effect on substrate warpage although average Cu percentages for top and bottom Cu layers are same. By proper distribution of Cu areas on a plane, warpage of the package can be modified. Simulation results of substrate warpage obtained using this cell model are much close to the experimental results. This method is less time consuming and requires less computation time than the actual model with details Cu traces.

[1]  Seunghyun Cho,et al.  Estimation of warpage and thermal stress of IVHs in flip-chip ball grid arrays package by FEM , 2008, Microelectron. Reliab..

[2]  J.J. Shea,et al.  Electronic packaging materials and their properties , 2001, IEEE Electrical Insulation Magazine.

[3]  S. Sitaraman,et al.  Methodology for modeling substrate warpage using copper trace pattern implementation , 2009, 2008 58th Electronic Components and Technology Conference.

[4]  Seunghyun Cho,et al.  New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board , 2010, Microelectron. Reliab..

[5]  Yuxiang Luo,et al.  Effects of package design on top PoP package warpage , 2008, 2008 58th Electronic Components and Technology Conference.

[6]  K. Moon,et al.  Methodology to Predict Substrate Warpage and Different Techniques to Achieve Substrate Warpage Targets , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[7]  Patrick B. Hassell,et al.  Measurement of thermally induced warpage of BGA packages/substrates using phase-stepping shadow moire , 1997, Proceedings of the 1997 1st Electronic Packaging Technology Conference (Cat. No.97TH8307).