A novel median based image impulse noise suppression system using spiking neurons on FPGA

ABSTRACT The most common impulse noise suppression methods are based on the median filter. They are suitable for low noise densities, but employing a separate noise detection step makes them suitable for higher noise rates. Instead, this may degrade the performance for lower noise. Particularly, the adaptive median noise removal algorithm improves the results for both low and high noise corruption rates. This paper presents a novel noise detection and filtering algorithm that uses leaky integrate and fire spiking neurons which model natural computing of the brain. In the proposed method, at each process of the detection and the filtering, all pixels of an adaptive sliding window are fed to the spiking neurons performing the operations in parallel. As a result, higher processing speed and higher operating frequency are achieved. An FPGA is used to implement the algorithm due to its real-time application and reconfigurable structure. The proposed architecture represents a slight increase in the PSNR values, whereas it consumes less hardware resources compared to the previous works. The design is implemented on Cyclone IV device from Altera family. It includes 3231 LUTs and the maximum operating frequency of 187 MHz is achieved.