A reduced hardware general purpose systolic array design

Although there may be many general purpose systolic array design and implementation which could be used to configure some special systolic structure, the degree of their hardware complexity and flexibility is a main question. In this paper we have designed a new systolic array system to realize a range of various algorithms without increasing the hardware structure significantly. The proposed concepts that have been used are: 1) using a novel architecture to allow any number of desired time delays along the data path; 2) dividing instructions and data into two formats-tagged and untagged formats; and 3) suitable processing element (PE) architecture design.