Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (<i>V</i><sub>th</sub>) roll-off characteristics at supply voltage (<i>V</i><sub>DD</sub>) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (<i>N</i><sub>ch</sub>) and Fin height (<i>H</i>)/width (<i>W</i>) on device <i>V</i><sub>th</sub> are also compared. In addition, the <i>V</i><sub>th</sub> of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (<i>N</i><sub>sub</sub>). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (<i>t</i><sub>HL</sub>) and low-to-high delay time (<i>t</i><sub>LH</sub>) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

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