Comparative analysis of process variation impact on flip-flops soft error rate

Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.

[1]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[2]  Narayanan Vijaykrishnan,et al.  Analysis of soft error rate in flip-flops and scannable latches , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[3]  Takashi S. Nakamura,et al.  Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices , 2008 .

[4]  Narayanan Vijaykrishnan,et al.  Effect of Power Optimizations on Soft Error Rate , 2003, VLSI-SoC.

[5]  Keith A. Bowman,et al.  Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[6]  Ashutosh Das,et al.  A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .

[7]  Kartik Mohanram,et al.  Cost-effective radiation hardening technique for combinational logic , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[8]  M. Baze,et al.  Attenuation of single event induced pulses in CMOS combinational logic , 1997 .

[9]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[10]  Mohamed I. Elmasry,et al.  Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[11]  T. P. Ma,et al.  Ionizing radiation effects in MOS devices and circuits , 1989 .

[12]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[13]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[14]  Philippe Roche,et al.  Factors that impact the critical charge of memory elements , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[15]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[16]  Rong Luo,et al.  Impact of process variation on soft error vulnerability for nanometer VLSI circuits , 2005, 2005 6th International Conference on ASIC.

[17]  Atsushi Kurokawa,et al.  Challenge: variability characterization and modeling for 65- to 90-nm processes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[18]  Narayanan Vijaykrishnan,et al.  Variation Impact on SER of Combinational Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[19]  Rong Luo,et al.  Modeling the Impact of Process Variation on Critical Charge Distribution , 2006, 2006 IEEE International SOC Conference.

[20]  Tino Heijmen.  Soft-Error Vulnerability of Sub-100-nm Flip-Flops , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[21]  F. Klass.  Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[22]  R. Baumann.  Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[23]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).