Embedded Silicon Fan-Out (eSiFO®) Technology for Wafer-Level System Integration

[1]  Curtis Zwenger,et al.  Silicon Wafer Integrated Fan-out Technology , 2015 .

[2]  John H. Lau Patent issues of embedded fan-out wafer/panel level packaging , 2016, 2016 China Semiconductor Technology International Conference (CSTIC).

[3]  Lixi Wan,et al.  Reliability of Ultra-Thin Embedded Silicon Fan-Out (eSiFO) Package Directly Assembled on PCB for Mobile Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[4]  Hai-Young Lee,et al.  Ultra-Wideband CPW-to-Substrate Integrated Waveguide Transition Using an Elevated-CPW Section , 2008, IEEE Microwave and Wireless Components Letters.

[5]  Vempati Srinivasa Rao,et al.  Development of Package-on-Package Using Embedded Wafer-Level Package Approach , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[6]  Jianmin Miao,et al.  Effect of SF 6 flow rate on the etched surface profile and bottom grass formation in deep reactive ion etching process , 2006 .

[7]  Daquan Yu,et al.  Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for Multi-chip and 3D System Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).